The requirements to forming such interconnect in a through-hole is the compatibility with further processing to manufacture the integrated circuit. This includes both front-end processing, such as needed for the definition of electrical elements and the forming of metallization layers, and back-end processing, which are also known as assembly processes. Moreover, the interconnect should meet product reliability requirements. Suitably, the through-hole is formed from the second side with one or more etching techniques. Therewith, the metallization layer is exposed. Then, electrically conductive material is provided so as to form the via. Several techniques such as sputtering, chemical vapour deposition and electroplating may be used alternatively and/or in combination. It has been found in experiments that the adhesion of the electrically conductive layer to the substrate does not always meets the reliability requirements. Adhesion is known to be an issue in industrialisation of new semiconductor processes. Several factors may cause insufficient adhesion, and combination effects are herein not to be excluded. Good adhesion is in other words an engineering challenge.
It is therefore an object of the invention to provide a method which allows good adhesion.
This object is achieved by forming an amorphous silicon layer prior to deposition of the electrically conductive layer. The conductive layer is chosen so as to prevent damage to the amorphous silicon layer. The amorphous silicon layer is found suitable for provision of good adhesion, if it is not subsequently damaged. Such damage may occur if it reacts. Now, a conventional adhesion layer such as sputtered titanium, has a very high reactivity towards amorphous silicon. This may cause so-called Kirkendall voiding, which deteriorates the adhesion.
Suitably, the amorphous silicon layer has a thickness of less than 10 um, preferably even less than 3 um. This decreases the size of any voids formed nevertheless. It is understood that the term ‘amorphous silicon layer’ does not exclude the presence of any polycrystalline regions within the amorphous silicon layer.
Most favourably, the conductive layer comprises a protection layer for the amorphous silicon. Suitably, this is a nickel layer. Particularly in combination with the nickel layer, use of silver has turned out very beneficial The amorphous silicon layer is preferably formed by sputter etching technique. The step of sputter etching may be combined with the removal of any native oxide on the metallization layer.